1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it relates to a semiconductor device formed on an SOI substrate and a method of manufacturing the same.
2. Description of the Background Art
In a conventional MOS field-effect transistor (MOSFET: hereinafter referred to as a MOS transistor) formed on an SOI substrate having a buried oxide film formed on a silicon substrate and an SOI (silicon on insulator) layer formed on the buried oxide film, a phenomenon called a DIBL (drain induced barrier lowering) effect is now coming into question due to refinement of elements.
FIG. 65 typically shows a sectional structure of a conventional MOS transistor Q1 formed on a conventional SOI substrate 1.
The SOI substrate 1 has a buried oxide film 3 formed on a silicon substrate 2 and an SOI layer 4 formed on the buried oxide film 3. A channel region 7 is arranged in the SOI layer 4 with a drain region 5 and a source region 6 arranged on both sides thereof, while a gate electrode 9 is arranged above the channel region 7 through a gate insulator film 8 to form the MOS transistor Q1. The MOS transistor Q1 is an n-channel transistor.
When applying voltages to the gate electrode 9 and the drain region 5 in such a MOS transistor Q1, a potential barrier in the vicinity of the source region 6 lowers and electrons flow from the source region 6 to the drain region 5 through a channel formed in the channel region 7. While this is a normal operation, the DIBL effect is a phenomenon lowering the potential barrier of a p-n junction of the source region 6 and lowering the threshold voltage of the transistor Q1 due to application of a high voltage to the drain region 5. Particularly in the MOS transistor Q1 formed on the SOI substrate 1 shown in FIG. 65, the DIBL effect remarkably appears due to an operation in a state electrically floating the channel region 7 and an electric field (referred to as a drain electric field) sneaking up on the source region 6 from the drain region 5 through the buried oxide film 3 as shown by arrows in FIG. 65, to result in a problem. It is particularly important for a MOS transistor formed on an SOI substrate to solve the problem of the DIBL effect.
FIGS. 66A and 66B typically show the DIBL effect. FIG. 66A is a model diagram of the MOS transistor Q1, and FIG. 66B is a conceptual diagram of a potential barrier PB.
As shown in FIG. 66B, the potential barrier PB is held and no electrons flow out from the source region 6 when a drain voltage V.sub.D is zero as shown on a characteristic curve A. When the drain voltage V.sub.D is supplied, however, the value of the potential barrier PB reduces in response to the drain voltage V.sub.D.
Referring to FIG. 66B, the drain voltage V.sub.D is relatively small on a characteristic curve B and relatively large on a characteristic curve C. Thus, it follows that the potential barrier PB reduces due to a drain electric field to lower the threshold even if no voltage is supplied to the gate electrode 9. When the potential barrier PB reduces beyond a certain extent, electrons flow out from the source region 6 toward the drain region 5 even if no voltage is supplied to the gate electrode 9, to disadvantageously disable the gate electrode 9 from a switching operation.
Particularly in a short-channel MOS transistor having a short channel length developed in view of refinement of the element, the drain electric field relatively strengthens and hence influence by the DIBL effect is further serious.
Following improvement of the degree of integration, further, it is apprehended that an operation of an adjacent element exerts influence on a MOS transistor as shown below.
FIG. 67 is a plan view showing two MOS transistors Q1 and Q2 as viewed from above gate electrodes 9 and 91. The gate electrodes 9 and 91 of the MOS transistors Q1 and Q2 are arranged perpendicularly to each other, and a drain region 51 (a source region 61 is provided through the gate electrode 91) of the MOS transistor Q2 is arranged in parallel with a drain region 5, a source region 6 and a channel region 7 of the MOS transistor Q1 through an element isolation film IR.
FIG. 68 is a sectional view taken along the line X--X in FIG. 67. As shown in FIG. 68, the drain region 51 of the MOS transistor Q2 is opposed to the channel region 7 of the MOS transistor Q1 through the element isolation film IR formed by a silicon oxide film. When a drain voltage V.sub.D1 is applied to the drain region 51, therefore, a drain electric field sneaks up on the source region 6 through a buried oxide film 3 to induce electrons on an edge portion of the channel region 7, and the electrons cause current leakage of the MOS transistor Q1. Further, part of the drain electric field passing through the element isolation film IR also induces electrons on the edge portion of the channel region 7.
Particularly under such present circumstances that the distance between the MOS transistors Q1 and Q2, i.e., a distance L shown in FIG. 67 is getting shorter following improvement of the degree of integration, the problem of current leakage (referred to as edge leakage) from the edge portion of the channel region 7 is an unignorable phenomenon. Also when a diode is formed in place of the MOS transistor Q2, a similar phenomenon occurs due to a voltage applied to a semiconductor region of the diode.
This phenomenon similarly occurs also in a MOS transistor formed on a bulk silicon substrate.